A semiconductor structure includes a substrate, including a first region, a second region, and a third region between the first region and the second region; a first fin structure including first nanowires disposed over the first region; a second fin structure including second nanowires disposed over the second region; and a first doped layer, disposed over the third region and in contact with each first nanowire and each second nanowire. The first and second nanowires are respectively arranged along a direction perpendicular to the surface of the substrate and both contain first doping ions. The first doped layer contains second doping ions with a type opposite to the type of the first doping ions. The semiconductor structure includes a source doped layer over the first region; a drain doped layer over the second region; and a first gate structure, disposed across the first fin structure and surrounding each first nanowire.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a sheet that is a semiconductor. In an embodiment a length dimension of the sheet and a width dimension of the sheet are greater than a thickness dimension of the sheet. In an embodiment, a gate structure is around the sheet, and a first spacer is adjacent to a first end of the gate structure, and a second spacer adjacent to a second end of the gate structure. In an embodiment, a source contact is around the sheet and adjacent to the first spacer, and a drain contact is around the sheet and adjacent to the second spacer.

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.

An integrated circuit semiconductor device includes a first region including first active fins extending in a first direction, and first transistors including first gate electrodes extending in a second direction, a second region in contact with the first region in the second direction, wherein the second region includes second active fins extending in the first direction, and second transistors including second gate electrodes extending in the second direction. The integrated circuit semiconductor device includes metal dams at a boundary of the first region and the second region to separate the first gate electrodes and the second gate electrodes in the second direction, wherein the metal dams, the first gate electrodes, and the second gate electrodes are electrically connected in the second direction.

A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.

A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.

A method includes forming a first semiconductor fin on a substrate, forming a source/drain region in the first semiconductor fin, depositing a capping layer on the source/drain region, where the capping layer includes a first boron concentration higher than a second boron concentration of the source/drain region, etching an opening through the capping layer, the opening exposing the source/drain region, forming a silicide layer on the exposed source/drain region and forming a source/drain contact on the silicide layer.