An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.

A semiconductor device includes a semiconductor substrate and a power transistor having a plurality of transistor cells. Each transistor cell includes: a gate trench structure formed in the semiconductor substrate and circumscribing the transistor cell; a needle-shaped field electrode trench structure formed in the semiconductor substrate and spaced inward from the gate trench structure; a source region of a first conductivity type formed in the semiconductor substrate adjacent the gate trench structure; a body region of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate below the source region; and a drift zone of the first conductivity type formed in the semiconductor substrate below the body region. The semiconductor device further includes a plurality of MOS-gated diodes or Schottky diodes, each diode formed in a non-active area of the power transistor between adjacent ones of the transistor cells. Corresponding methods of manufacture are also described.

Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first well region and a second well region in the semiconductor substrate; and forming a first gate structure on a surface of the second well region and a portion of a surface of the first well region and a second gate structure on a portion of the first well region. A first opening is formed between the first gate structure and the second gate structure. The method also include forming a sidewall spacer layer covering sidewall and bottom surfaces of the first opening in the first opening; forming a dielectric layer on the semiconductor substrate to cover the first gate structure, the second gate structure and the sidewall spacer layer; and forming a floating plug in the dielectric layer and on the sidewall spacer layer.

In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.

A new transistor structure is disclosed. This new structure has a dielectric stress layer in a three-dimensional structure outside of the gate region for modulation or the characteristics of the transistor. Additionally, trenches are created in the region between the source electrode and the drain electrode in such a manner so as to create ridges that traverse the gate region.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

According to the embodiment of the invention, the semiconductor device includes a semiconductor member, a first electrode, a second electrode, a third electrode, a first conductive member, and a first insulating member. The first semiconductor member includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region includes one of a first material and a second material. The third semiconductor region is provided between at least a part of the first semiconductor region and the second semiconductor region. The first electrode is electrically connected with the first semiconductor region. The second electrode is electrically connected with the second semiconductor region. At least a part of the third semiconductor region is between an other portion of the third electrode and the first conductive member. At least a part of the first insulating member is between the third electrode and the semiconductor member.