The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a gate structure being provided on a surface of the substrate, and a source region and a drain region being provided in the substrate at two sides of the gate structure, respectively; and a contact located on the substrate, the contact including a first contact located on the substrate and a second contact located on a side of the first contact away from the substrate, in which an area of a bottom surface of the first contact is greater than an area of a top surface of the second contact.

Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.

A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures.