A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

A stacked ESD structure comprises a heavily doped substrate; an epitaxial layer grown on the substrate; a trench formed in the epitaxial layer; an oxide layer formed on an inner sidewall of the trench; first and second poly layers formed in the trench; a plurality of P-type regions and N-type regions formed inside the first and second poly layers to make back to back diodes in the first and second poly layers respectively; a dielectric layer formed in the trench, between the first and second poly layers; an insulating layer formed on top of the second poly layer and the trench; a plurality of contact defined to connect the first poly layer, the poly resistor and the second poly layer, through the insulating layer; and a metal layer formed on top of the insulating layer.

A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

Disclosed are apparatuses and related methods for fabrication. The apparatus includes a field-effect transistor (FET). The FET has a source contact coupled to a source implant in a body layer, a drain contact coupled to a drain implant in the body layer, and a first gate coupled to a transistor channel in the body layer between the source contact and the drain contact. The FET further includes a second gate coupled to the body layer between the source contact and the drain contact, a drift region in the body layer, where the second gate at least partially overlaps the drift region, and a resurf portion disposed partially over the first gate and over the second gate.

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

A semiconductor device that includes: a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate in a vertical direction relative to the substrate, wherein the first source/drain layer includes a first source/drain region on an outer side of the substrate in a transverse direction, and a first body region on an inner side of the first source/drain region in the transverse direction; a gate stack surrounding a part of the channel layer; a back gate under the channel layer, wherein in a top view, the back gate, the first body region in the first source/drain region and the channel layer at least partially overlap; a back gate dielectric layer between the first source/drain layer and the back gate; and a back gate contact portion, the back gate contact portion is configured to apply a bias to the back gate.

The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.

A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.