A semiconductor device includes a substrate; a 1.sup.st transistor formed above the substrate, and having a 1.sup.st transistor stack including a plurality of 1.sup.st channel structures, a 1.sup.st gate structure surrounding the 1.sup.st channel structures, and 1.sup.st and 2.sup.nd source/drain regions at both ends of the 1.sup.st transistor stack in a 1.sup.st channel length direction; and a 2.sup.nd transistor formed above the 1.sup.st transistor in a vertical direction, and having a 2.sup.nd transistor stack including a plurality of 2.sup.nd channel structures, a 2.sup.nd gate structure surrounding the 2.sup.nd channel structures, and 3.sup.rd and 4.sup.th source/drain regions at both ends of the 2.sup.nd transistor stack in a 2.sup.nd channel length direction, wherein the 3.sup.rd source/drain region does not vertically overlap the 1.sup.st source/drain region or the 2.sup.nd source/drain region, and the 4.sup.th source/drain region does not vertically overlap the 1.sup.st source/drain region or the 2.sup.nd source/drain region.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a front end of line (FEOL) structure, and a metallization structure. The FEOL structure is disposed over the substrate. The metallization structure is over the FEOL structure. The metallization structure includes a transistor structure, an isolation structure, and a capacitor. The transistor structure has a source region and a drain region connected by a channel structure. The isolation structure is over the transistor structure and exposing a portion of the source region, and a side of the isolation structure has at least a lateral recess vertically overlaps the channel structure. The capacitor is in contact with the source region and disposed conformal to the lateral recess. A method for manufacturing a semiconductor structure is also provided.

A semiconductor structure and a forming method thereof are provided. One form of a semiconductor structure includes: a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure located on the first substrate, a first device gate structure extending across the first channel layer structure, and a first source-drain doping region located in the first channel layer structure on two sides of the first device gate structure; and a second device structure, located on a front surface of the first device structure, including a second substrate located on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure located on the second substrate, a second device gate structure extending across the second channel layer structure, and a second source-drain doping region located in the second channel layer structure on two sides of the second device gate structure, where projections of the second channel layer structure and the first channel layer structure onto the first substrate intersect non-orthogonally. The electricity of the first device can be led out according to the present disclosure.

A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

A display module and a method for manufacturing the same are provided. The display module manufacturing method includes: forming a semiconductor pattern on a substrate; forming a first insulating layer covering the semiconductor pattern on the substrate; forming a gate electrode on a region of the first insulating layer corresponding to a gate region of the semiconductor pattern; forming a second insulating layer covering the gate electrode on the first insulating layer; forming a first hole passing through the first insulating layer and the second insulating layer to expose a drain region of the semiconductor pattern and forming a second hole passing through the first insulating layer and the second insulating layer to expose a source region of the semiconductor pattern; and forming a first barrier pattern on the drain region in the first hole and a second barrier pattern on the source region in the second hole, and forming a drain electrode on the first barrier pattern and a source electrode on the second barrier pattern.

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.