NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

A transient-voltage-suppression protection device and a manufacturing process therefor, and an electronic product. The transient-voltage-suppression protection device includes a substrate, a first trap, a second trap, a first injection region, and a second injection region, where the first trap and the second trap are sequentially arranged on the substrate from left to right at an interval, have a same doping type that is opposite to a doping type of the substrate, and are respectively provided with the first injection region and the second injection region with opposite doping types. The electronic product includes the transient-voltage-suppression protection device. In the solutions described, protection can be triggered and started at a lower voltage; the capacitance is small, and the manufacturing process is simple.

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The present invention breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an i.sup.th state, and 1 <i <M . The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.