A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Embodiments described herein relate to a method for manufacturing a 1.5T SONOS flash memory. First, a first polysilicon gate layer is deposited and formed on a semiconductor substrate, then a formation area of a memory gate is defined on the first polysilicon gate layer, polysilicon in the formation area of the memory gate is etched away, and etching is stopped on a gate oxide layer. Next, an ONO layer and a second polysilicon gate layer are sequentially deposited, chemical mechanical polishing is performed on the second polysilicon gate layer, the ONO layer remaining on the top of the first polysilicon gate layer is cleaned away, and then gate structures of a logic device and a 1.5T SONOS device are formed at the same time.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

A device includes an active region, a select gate, a control gate, a first metal alloy layer, and a second metal alloy layer. The active region has a source region and a drain region. The select gate is over the active region and between the source region and the drain region. The control gate is over the active region and between the source region and the select gate. The first metal alloy layer is in contact with the source region. The second metal alloy layer is in contact with the drain region and higher than a top surface of the control gate.

Channel material is conformally deposited along sidewalls of one or more etched features of a mold stack in fabricating a three-terminal memory device. The channel material is deposited in recessed regions and non-recessed regions of the one or more etched features. A sacrificial liner is deposited on the channel material. A directional etch removes the sacrificial liner from non-recessed regions of the one or more etched features. An isotropic etch removes the channel material from non-recessed regions of the one or more etched features, leaving the channel material and the sacrificial liner intact in the recessed regions. The sacrificial liner is removed, leaving the channel material intact and isolated with minimal loss of channel material from over-etch.

A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.