A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing processing steps to form first memory cells within the second level and form second memory cells within the third level, where the first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and then at performing at least one deposition step which deposits gate electrodes for both the second and the third transistors, and forming at least four independent memory arrays.

A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.

A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate.

A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a second level including a plurality of second transistors, where the second level overlays the first level, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the plurality of second transistors is at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method of making a semiconductor device includes depositing an isolation region between adjacent fins of a plurality of fins over a substrate, wherein a top-most surface of the isolation region is a first distance from a bottom of the substrate. The method further includes doping each of the plurality of fins with a first dopant having a first dopant type to define a first doped region in each of the plurality of fins, wherein a bottom-most surface of the first doped region is a second distance from the bottom of the substrate, and the second distance is greater than the first distance. The method further includes doping each of the plurality of fins with a second dopant having a second dopant type to define a second doped region in each of the plurality of fins, wherein the second doped region contacts the isolation region.

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, where the bonded includes at least one oxide to oxide bond, and where the bonded includes at least one metal to metal bond.