A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.

A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

The present invention discloses an electronic device formed of a group III nitride. In one embodiment, a substrate is fabricated by the ammonothermal method and a drift layer is fabricated by hydride vapor phase epitaxy. After etching a trench, p-type contact pads are made by pulsed laser deposition followed by n-type contact pads by pulsed laser deposition. The bandgap of the p-type contact pad is designed larger than that of the drift layer. Upon forward bias between p-type contact pads (gate) and n-type contact pads (source), holes and electrons are injected into the drift layer from the p-type contact pads and n-type contact pads. Injected electrons drift to the backside of the substrate (drain).

A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.