A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.

A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.

A semiconductor device including a semiconductor substrate having an edge termination portion and an active portion is provided. The edge termination portion includes an outer edge region provided on an end portion of a front surface of the semiconductor substrate and within a predetermined depth range. The active portion includes a well region provided on an inner side relative to the outer edge region of the front surface of the semiconductor substrate and within a predetermined depth range. The semiconductor device further includes an insulating film provided on the front surface of the semiconductor substrate and at least between the outer edge region and the well region and having a taper portion, and a resistive film provided on the insulating film and electrically connected to the outer edge region and the well region. A taper angle of the taper portion of the insulating film is 60 degrees or less.

The present disclosure relates to a system for biasing a power amplifier. The system can include a first die that includes a power amplifier circuit and a passive component having an electrical property that depends on one or more conditions of the first die. Further, the system can include a second die including a bias signal generating circuit that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die.

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

A semiconductor device including a semiconductor substrate having an edge termination portion and an active portion is provided. The edge termination portion includes an outer edge region provided on an end portion of a front surface of the semiconductor substrate and within a predetermined depth range. The active portion includes a well region provided on an inner side relative to the outer edge region of the front surface of the semiconductor substrate and within a predetermined depth range. The semiconductor device further includes an insulating film provided on the front surface of the semiconductor substrate and at least between the outer edge region and the well region and having a taper portion, and a resistive film provided on the insulating film and electrically connected to the outer edge region and the well region. A taper angle of the taper portion of the insulating film is 60 degrees or less.

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.

A semiconductor device and a method of making the same is provided. The device includes a semiconductor substrate having a major surface and a back surface. The device also includes a bipolar transistor. The bipolar transistor has comprises a collector region located in the semiconductor substrate; a base region located within the collector region and positioned adjacent the major surface; an emitter region located within the base region and positioned adjacent the major surface; and a collector terminal located on the major surface of the semiconductor substrate. The collector terminal includes: a first electrically conductive part electrically connected to the collector region; an electrically resistive part electrically connected to the first electrically conductive part, and a second electrically conductive part for allowing an external electrical connection to be made the collector terminal. The second conductive part is electrically connected to the first conductive part via the resistive part.

Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are described. An example apparatus includes a first layout region including a first transistor area including at least one first transistor, at least one contact in proximity to the first transistor area, and a first resistor area comprising at least one first resistor coupled to the at least one first transistor. The first transistor area and the at least one contact are aligned in a first direction, and the first transistor area and the first resistor area are aligned in a second direction. The second direction may be substantially perpendicular to the first direction. The at least one contact may be one of a substrate contact and a well contact.