A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.

Example implementations include a bandgap voltage device with a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first proportional-to-absolute-temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and operatively coupled to the bandgap output node, and a second current source operatively coupled to the current mirror and operable to output a second PTAT current. Example implementations also include a bandgap transistor device with a first P+ layer proximate to a center of a planar surface of a transistor device, a first N+ layer at least partially surrounding the first P+ layer along the planar surface, a second P+ layer at least partially surrounding the first N+ layer along the planar surface, a second N+ layer at least partially surrounding the second P+ layer along the planar surface, and a third P+ layer at least partially surrounding the second N+ layer along the planar surface.

A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n.sup.+ buried region has a floating potential. An n-type body region is located on a first surface side of the n.sup.+ buried region. A p.sup.+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p.sup.+ drain region is located in the first surface spacedly from the p.sup.+ source region. A p-type impurity region PIR is located between the n.sup.+ buried region and the n-type body region and isolates the n.sup.+ buried region and the n-type body region from each other.

In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

The present disclosure provides a semiconductor device that prevents a resistor component connected in series with a base electrode from the electrostatic damage. A semiconductor device includes, a collector layer, which is a first conductivity type semiconductor, a base layer, which is a second conductivity type semiconductor and connected with the collector layer, an emitter layer, which is the first conductivity type semiconductor and connected with the base layer, a first electrode, electrically connected to the base layer, a first resistor component, connected in series with the first electrode in a conductive path connecting the first electrode and the base layer, a second electrode, electrically connected to the emitter layer and the first resistor component; and a protection component, connected to the first electrode in parallel with the first resistor component, wherein the protection component comprises a pair of diodes formed by a pn junction and by a way of making both ends of the conductive path into a same polarity.

A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.

A characteristic of a semiconductor device having a back electrode including an AuSb alloy is improved. The semiconductor device has a semiconductor substrate and the back electrode including the AuSb alloy layer. The back electrode is formed on the semiconductor substrate. The Sb concentration in the AuSb alloy layer is equal to or greater than 15 wt %, and equal to or less than 37 wt %. The thickness of the AuSb alloy layer is equal to or larger than 20 nm, and equal to or less than 45 nm.

The present disclosure relates to a bipolar transistor semiconductor device including: a substrate layer, a collector epitaxial layer supported by the substrate layer, a base region supported by a portion of the collector epitaxial layer, and an emitter region supported by a portion of the base region. The emitter region includes a polysilicon material.

In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.