A method for manufacturing a semiconductor device includes forming a source and region in a substrate. A core channel region is formed adjacent the source region. A barrier layer is formed adjacent the core channel region. A drain region is formed in the substrate such that the barrier layer is between the core channel region and the drain region. A first portion of a shell is formed along the core channel region. A second portion of the shell is formed along the barrier layer. The second portion of the shell includes a different material than the first portion of the shell.

A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region. The barrier layer is between the core channel region and the drain region. The barrier layer is a graded doped barrier layer.

A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

Provided are: injection control regions of a second conductivity type provided on a charge transport region of a first conductivity type; main electrode regions of the first conductivity type provided on the injection control regions; insulated gate electrode structures going through the main electrode region and the injection control regions in the depth direction; an injection suppression region going through the main electrode regions and the injection control regions in the depth direction so as to form a pn junction in a path leading to the charge transport region, the injection suppression region including a semiconductor material with a narrower bandgap than a material of the charge transport region; and a contact protection region of the second conductivity type contacting the bottom surface of the injection suppression region.

An electronic or optoelectronic device includes: (1) a layer of a first material; and (2) a layer of a second material disposed on the layer of the first material, wherein the first material is different from the second material, and the layer of the first material is spaced from the layer of the second material by a gap.

A device includes a controllable current source connected between a first node and a first terminal coupled to a cathode of a controllable diode. A capacitor is connected between the first node and a second terminal coupled to an anode of the controllable diode. A first switch is connected between the first node and a third terminal coupled to a gate of the controllable diode. A second switch is connected between the second and third terminals. A first diode is connected between the third terminal and the second terminal, an anode of the first diode being preferably coupled to the third terminal.

Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region, The barrier layer is between the core channel region and the drain region, The barrier layer is a graded doped barrier layer.

A Z2-FET-type structure includes a first front gate, a second front gate, a first back gate doped with p-type dopants, and a second back gate doped with n-type dopants. The structure may also include a buried insulating layer between the front gates and the back gates, an anode region, a cathode region, and an intermediate region separating the anode region and the cathode region.

Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.