A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance. The high withstand voltage LDMOS is characterizing in including: a first electroconductive type body region formed on a main surface of a semiconductor substrate; a second electroconductive type source region formed on a surface of the body region; a second electroconductive type drift region formed so as to have contact with the body region; a second electroconductive type drain region formed on the drift region; a first electroconductive type buried region having contact with the body region and formed below the drift region; a gate electrode formed above the body region between the source region and the drift region and above the drift region nearer to the source region via a gate insulating film; a first field plate that extends from the gate electrode toward the drain region and that is formed above the drift region via a first insulating film; and a second field plate that has contact with the source region or the gate electrode and that is formed above the first field plate via a second insulating film, in which a distance between the buried region and the drain region is smaller than a distance between the first field plate and the drain region and larger than a distance between the second field plate and the drain region.

A gate controlled semiconductor device comprising a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region. The device further comprises at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region. The device further comprises at least one active trench extending from a surface into the drift region, in which the at least one first contact region adjoins the at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region. The at least one active trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises different thicknesses; at least one auxiliary trench extending from the surface into the drift region. The at least one auxiliary trench comprises: two vertical sidewalls and a bottom surface between the two vertical sidewalls; and an insulation layer along the vertical side walls and the bottom surface, wherein the insulation layer along at least one vertical side wall comprises a constant thickness.

A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.

There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a drift region having a first conductivity type situated over an anode layer having a second conductivity type. The device also includes first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bordered by a cathode diffusion having the first conductivity type. In addition, the device includes an inter-trench structure situated in the drift region between the first and second control trenches. The inter-trench structure includes one or more first conductivity regions having the first conductivity type and one or more second conductivity region having the second conductivity type, the one or more first conductivity regions and the one or more second conductivity regions configured to substantially charge-balance the inter-trench structure.

Disclosed are a semiconductor device, a preparation method therefor and electrical equipment thereof. The semiconductor device includes: a silicon substrate on which an emitter, a gate, and a collector are formed; a bootstrap electrode formed on the silicon substrate; and an insulating layer, formed on the silicon substrate and disposed between the emitter and the bootstrap electrode. A bootstrap capacitor is formed between the emitter and the bootstrap electrode.

Embodiments of the disclosure provide a bipolar junction transistor (BJT) structure and related method. A BJT according to the disclosure may include a base over a semiconductor substrate. A collector is over the semiconductor substrate and laterally abuts a first horizontal end of the base. An emitter is over the semiconductor substrate and laterally abuts a second horizontal end of the base opposite the first horizontal end. A horizontal interface between the emitter and the base is smaller than a horizontal interface between the collector and the base.

A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.

A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides a lower layer and an upper layer; forming an opening in the upper layer; forming a supplemental layer on the lower layer exposed in the opening; heat treating the lower electrode and the supplemental layer; covering at least the upper layer of the lower electrode with an insulating film; and forming an upper electrode in an area on the insulating film, where the area is not overlapped with the supplemental layer and within 100 μm at most from the supplemental layer. A feature of the MIM capacitor is that the supplemental layer is made of a same metal as a metal contained in the lower layer of the lower electrode.