A power diode comprises a plurality of diode cells (10). Each diode cell (10) comprises a first conductivity type first anode layer (40), a first conductivity type second anode layer (45) having a lower doping concentration than the first anode layer (40) and being separated from an anode electrode layer (20) by the first anode layer (40), a second conductivity type drift layer (50) forming a pn-junction with the second anode layer (45), a second conductivity type cathode layer (60) being in direct contact with the cathode electrode layer (60), and a cathode-side segmentation layer (67) being in direct contact with the cathode electrode layer (30). A material of the cathode-side segmentation layer (67) is a first conductivity type semiconductor, wherein an integrated doping content of the cathode-side, which is integrated along a direction perpendicular to the second main side (102), is below 2.Math.10.sup.13 cm.sup.?2, or a material of the cathode-side segmentation layer (67) is an insulating material. A horizontal cross-section through each diode cell (10) along a horizontal plane (K1) comprises a first area where the horizontal plane (K1) intersects the second anode layer (45) and a second area where the plane (K1) intersects the drift layer (50).

This invention discloses an insulating gate bipolar transistor (IGBT) device that comprises a substrate including a semiconductor layer of a first conductivity type on the top of the bottom semiconductor layer of a second conductivity type and supporting buried layer of a second conductivity type disposed below a top layer of the first conductivity type. The IGBT further has a plurality of MOS transistor cells each having a planar gate disposed on a top surface of the top layer wherein each of the planar gates extended between two adjacent body regions of the second conductivity type encompassing a emitter region of the first conductivity type wherein the body regions and emitter regions are near a top portion of the top layer of the first conductivity type. The IGBT further includes a trench gate vertically extending from the top portion of the top layer adjacent to a body region downwardly to the buried layer of the second conductivity. Furthermore, the device includes lightly doped region in the top layer of the first conductivity type that is disposed next to the trench gate below the body region of the second conductivity type above the buried layer of the second conductivity type.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

A method for processing a semiconductor workpiece, including: forming a trench structure in a first region of a semiconductor workpiece, extending from a surface of the semiconductor workpiece to a first depth, forming at least one recess in a second region of the semiconductor workpiece laterally next to the first region, the recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece to a second depth less than the first depth; forming a material layer over the semiconductor workpiece, the material layer filling the trench structure and recess and covering the surface of the semiconductor workpiece in the first region and in the second region; and planarizing the semiconductor workpiece to partially remove the material layer in the first region and in the second region, wherein the material layer remains in the trench structure and in the at least one recess.

A vertical bidirectional insulated gate turn-off (IGTO) device includes a top half formed over a top surface of a substrate and a bottom half formed over the bottom surface of the substrate. A top electrode is formed over the top half, and a bottom electrode is formed over the bottom half. The layered structure forms vertical NPN and PNP transistors. Each half includes trenched gates. When a first polarity voltage is applied across the electrodes, one of the halves may be turned on by biasing its gates to conduct current between the top and bottom electrodes. When a voltage of an opposite polarity is applied across the electrodes, the other one of the halves may be turned on by biasing its gates to conduct current between the two electrodes. In one embodiment, biasing the gates increases the beta of the NPN transistor to turn on the device.

The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

A method of manufacturing a semiconductor integrated circuit, includes: forming a first well region having a second conductivity type in an upper portion of a support layer having a first conductivity type; forming an oxide film on the first well region by a thermal oxidation method to decrease a concentration of impurities at an top surface of top surface side of the first well region; removing the oxide film; forming a second well region having the first conductivity type in an upper portion of the first well region; and merging a semiconductor element having a main electrode region having the second conductivity type in the second well region.

According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

A silicon carbide semiconductor device includes: a drift region of a first conductivity type; a base region of a second conductivity type disposed on the drift region; a main electrode contact region of the first conductivity type selectively embedded in a top of the base region at a higher impurity density than the drift region; a trench having a round part on a top surface side of the main electrode contact region to a level that is shallower than a depth of the main electrode contact region, the trench going from the round part through the base region and having a bottom that reaches the drift region; and an insulated gate structure provided on an inner side of the trench. A smallest radius of curvature of the round part is greater than a relatively high impurity region of the main electrode contact region.

A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.