A semiconductor device includes a body, a gate oxide layer, and a gate electrode. The body is defined by a drift region and one or more implant regions. A junction field effect region is defined between one of the implant regions and another one of the implant regions. The gate oxide layer is grown as a single, unitary structure extending across the semiconductor body and at least partially overlap the implant regions. The gate oxide layer is additionally defined by a central expansion region between the implant regions, and extend into the junction field effect region. A gate electrode is disposed on the gate oxide layer.

The present application discloses a super junction device, comprising: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; wherein a trench-filling super junction structure is formed on the N-type buffer layer; a backside structure of the super junction device comprises a drain region; the N-type semiconductor substrate is removed in a backside thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer; the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.

The present application discloses a super junction device, which includes: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; a trench filled super junction structure is formed on the N-type buffer layer; a back structure includes a drain region and a patterned back P-type impurity region; the N-type semiconductor substrate is removed in a back thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the back thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer, the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

A metal layer is deposited on a wafer that has silicon carbide, wherein the metal layer forms a contact face. A laser annealing is performed at the contact face using a laser beam application that causes the metal layer to react with the wafer and form a silicide layer. The laser beam has a footprint having a size. To laser anneal the contact face, a first portion of the contact face is irradiated, the footprint of the laser beam is moved by a step smaller than the size of the footprint, and a second portion of the contact face is irradiated, thereby causing the first portion and the second portion of the contact face to overlap.

A power semiconductor device includes a semiconductor body; a first load terminal at the semiconductor body; and a second load terminal at the semiconductor body. The power semiconductor device is configured to conduct a load current between the first load terminal and the second load terminal. The first load terminal has a first side and a second side adjoining the semiconductor body. The first load terminal includes: at the first side, an atomic layer deposition (ALD) layer; at the second side, a base layer including copper; and between the ALD layer and the base layer, a coupling layer that includes copper-silicon-nitride (CuSiN).

An object is to provide a semiconductor device that implements cost reduction as well as determination of withstand voltage characteristics. A semiconductor substrate includes a semiconductor element on the front surface thereof and a back surface electrode on the back surface thereof that controls the operation of the semiconductor element. A first electrode and a second electrode are provided in a terminal region outside an active region in which the semiconductor element is formed. An insulating film is provided between the first electrode and the second electrode. The second electrode is provided on an insulating interlayer film provided on the front surface of the semiconductor substrate. The first electrode is in contact with the front surface of the semiconductor substrate and is provided on the semiconductor substrate closer to an end portion thereof than the second electrode is, and is electrically connected to the back surface electrode.

The present disclosure can be applied to semiconductor devices and, in particular, relates to a MOSFET device made of silicon carbide and a method for manufacturing same. A metal-oxide film semiconductor field-effect transistor device of the present disclosure may comprise: a drain electrode; a substrate arranged on the drain electrode; an N-type drift layer arranged on the substrate; a current-spreading layer arranged on the drift layer; P-type well layers arranged on the current-spreading layer to define a channel; an N+ region arranged on the well layers; a damage prevention layer adjacent to the N+ region and having a lower N-type doping concentration than that of the N+ region; a P+ region arranged on one side of the channel; a gate oxide layer arranged on the current-spreading layer; a gate layer arranged on the gate oxide layer; and a source electrode arranged on the gate layer.

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; an electrode structure on or in the semiconductor substrate, the electrode structure including an electrode and an insulating material that separates the electrode from the semiconductor substrate; and a strain-inducing material embedded in the electrode. The electrode structure adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The electrode is under either tensile or compressive stress in the first direction. The strain-inducing material either enhances or at least partly counteracts the stress of the electrode in the first direction. Methods of producing the semiconductor device are also described.