A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

In a silicon carbide substrate including: a SiC substrate; and a first semiconductor layer, a second semiconductor layer and a drift layer that are epitaxial layers sequentially formed on the SiC substrate, an impurity concentration of the first semiconductor layer is lower than impurity concentrations of the SiC substrate and the second semiconductor layer, and the second semiconductor layer is formed to have a high impurity concentration or a large thickness.

A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.

A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off angle equal to or more than 0° and equal to or less than 8° with respect to a {0001} face and a second face facing the first face and having a 4H-SiC crystal structure; a gate electrode extending in a first direction parallel to the first face; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 10.sup.21 cm.sup.-3. Assuming that a first reference length in the first direction is 0.5 .Math.m, a surface roughness of a surface of the silicon carbide layer in a range of the first reference length is equal to or less than 1 nm.

Disclosed is a superjunction semiconductor device (1) and a method for manufacturing the same and, more particularly, to a superjunction semiconductor device (1) and a method for manufacturing the same seeking to improve breakdown voltage characteristics of the device by effectively dispersing a lateral electric field in a ring region R in the lower portion of an epitaxial layer by forming first conductivity type floating impurity-doped regions in the lower portion of the epitaxial layer in the ring region R under a p-rich condition.

A semiconductor device is described. The semiconductor device includes: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches. The contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates. In the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches. Methods of producing the semiconductor device are also described.

A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.

A silicon carbide MOS-gated semiconductor device comprises a silicon carbide substrate, a drift layer, a first doped region, a second doped region, a plurality of third doped regions, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a metal layer. The gate electrode comprises a gate bus region and an active region. The active region comprises a plurality of gate electrode openings. The two adjacent gate electrode openings have a minimum width (W.sub.g) which is satisfied the following formula:

W.sub.g>W.sub.jfet+2×L.sub.ch+2×L.sub.x

L.sub.ch represents a channel length of channel regions, W.sub.jfet represents a minimum width of JFET regions, and L.sub.x represents a minimum overlapping length between the gate electrode and the second doped region.

A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. The method includes implanting protons through the second surface into the semiconductor body. The method further includes implanting ions through the second surface into the semiconductor body. The ions are ions of a non-doping element having an atomic number of at least 9. Thereafter, the method further includes processing the semiconductor body by thermal annealing.