A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type formed on the semiconductor substrate and having a first conductivity type impurity concentration higher than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type formed above the first semiconductor layer, a first device region formed in the second semiconductor layer and configured to operate based on a first reference voltage, a second device region formed in the second semiconductor layer and configured to operate based on a second reference voltage, the second device region being spaced apart from the first device region, and a region isolation structure interposed between the first and second device regions and formed in a region extending from a front surface of the second semiconductor layer to the first semiconductor layer so as to electrically isolate the first and second device regions from each other.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).

A high withstand voltage isolation region has a first diffusion layer of a second conductivity type formed on a principal surface of a semiconductor substrate. The high withstand voltage MOS has a second diffusion layer of the second conductivity type formed on the principal surface of the semiconductor substrate. A low side circuit region has a third diffusion layer of a first conductivity type formed on the principal surface of the semiconductor substrate. A fourth diffusion layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate is formed on the principal surface of the semiconductor substrate exposed between the first diffusion layer and the second diffusion layer. The fourth diffusion layer extends from the high side circuit region to the low side circuit region and does not contact the third diffusion layer.

A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate. The method further includes forming a second one of the source and drain of the first doping polarity type in or on the first well, wherein the implanting includes directing at least a first beam of ions towards the first well at an angle substantially perpendicular to a surface plane of the substrate, and directing at least a second beam of ions towards the first well at an angle substantially offset from a surface normal of the substrate.

The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

A network device includes one or more circuit components. The one or more circuit components include a semiconductor substrate, a first device terminal and a second device terminal, a drift region, and a mobility modulator. Both device terminals are coupled to the semiconductor substrate, the second device terminal being spatially separated from the first device terminal. The drift region is disposed on the semiconductor substrate between the first device terminal and the second device terminal, the drift region being configured to allow a flow of charge-carriers between the first device terminal and the second device terminal. The mobility modulator is coupled to the drift region, the mobility modulator being configured to selectively apply a field across the drift region responsive to one or more modulation signals, so as to modulate a mobility of charge-carriers as a function of longitudinal position along the drift region.

A semiconductor device includes: a chip having a main surface; a first conductive type first region formed on a surface layer portion of the main surface; a second conductive type second region formed on a surface layer portion of the first region; a drain region formed on a surface layer portion of the second region; a source region formed on the surface layer portion of the first region at a distance from the second region; and a second conductive type floating region formed in the first region at a thickness position between a bottom portion of the first region and a bottom portion of the second region and being spaced apart from the bottom portion of the second region, wherein the floating region faces the second region with a portion of the first region interposed between the floating region and the second region.

A semiconductor device includes: an n.sup.−-type epitaxial layer having an element main surface; a p.sup.−-type body region, an n.sup.+-type source region, and n.sup.+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p.sup.+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.

A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.