The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

In an example, an integrated circuit includes a junction-gate field effect transistor (JFET), a current generator, a dynamic filter, and an output transistor. The JFET has a JFET gate, a JFET source, and a JFET drain, the JFET drain adapted to be coupled to a power supply. The current generator has a current generator input and current generator outputs, the current generator input coupled to the JFET source and a first of the current generator outputs coupled to the JFET gate. The dynamic filter has a dynamic filter input and a dynamic filter output, the dynamic filter input coupled to a second of the current generator outputs. The output transistor has an output transistor gate coupled to the dynamic filter output.

A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.

A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.