A semiconductor device includes a region of semiconductor material of a first conductivity type. A body region of a second conductivity type is in the region of semiconductor material. The body region includes a first segment with a first peak dopant concentration, and a second segment laterally adjacent to the first segment with a second peak dopant concentration. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and is configured to provide a second channel region in the second segment, and adjoins the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.

Disclosed are a semiconductor structure and method of forming the structure. The semiconductor structure includes an extended drain metal oxide semiconductor field effect transistor (EDMOSFET). The EDMOSFET includes, in the semiconductor layer, a body well, which has a source region therein, and a drain drift well, which abuts the body well and has a drain region therein. A trench gate structure is within the drain drift well positioned laterally between the body-drain drift junction and an internal shallow trench isolation (STI) region and the internal STI region is between the trench gate structure and the drain region. A primary gate structure is on the top surface of the semiconductor layer traversing the body-drain drift junction and optionally extending over the trench gate structure. Gate dielectric material physically separates gate conductor materials of the primary and trench gate structures. Optionally, the EDMOSFET includes more than one trench gate structure.

A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.

A semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type, a source region and a body contact region in the second semiconductor region. The semiconductor device also includes a channel region, in the second semiconductor region, located laterally between the source region and the first semiconductor region, a gate dielectric layer overlying both the channel region and a portion of the first semiconductor region, and a gate electrode overlying the gate dielectric layer. The semiconductor device further includes a conformal conductive layer covering an upper surface of the body contact region and a side surface of the source region.

A semiconductor device includes: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration different from the impurity concentration of the base region.

The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.