A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.

Integrated circuit (IC) structures including asymmetric, recessed source and drain regions and methods for forming are provided. In an example, the IC structure includes a substrate, a gate structure over the substrate, first and second spacers contacting respective, opposite sidewalls of the gate structure, and source and drain regions on opposite sides of the gate structure. In one configuration, the source region includes an upper source portion having a first lateral width, and a lower source portion having a second lateral width greater than the first lateral width, and the drain region includes an upper drain portion having a third lateral width, and a lower drain portion having a fourth lateral width that is substantially the same as the third lateral width.

The present application discloses a semiconductor device with an inverter and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; a first impurity region and a second impurity region respectively positioned on two sides of the gate structure and positioned in the substrate; a first contact positioned on the first impurity region and including a first resistance; a second contact positioned on the first impurity region and including a second resistance less than the first resistance of the first contact. The first contact is configured to electrically couple to a power supply and the second contact is configured to electrically couple to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact, and the second contact together configure an inverter.

An IC includes a first and second active areas (AA) with a second conductivity type, a source and drain region, and an LDD extension to the source and drain in the first AA having a first conductivity type. A first bent-gate transistor includes a first gate electrode over the first AA extending over the corresponding LDD. The first gate electrode includes an angled portion that crosses the first AA at an angle of 45° to 80°. A second transistor includes a second gate electrode over the second AA extending over the corresponding LDD including a second gate electrode that can cross an edge of the second AA at an angle of about 90°. A first pocket distribution of the second conductivity type provides a pocket region under the first gate electrode. A threshold voltage of the first bent-gate transistor is ≥30 mV lower as compared to the second transistor.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

A power device and a guard ring structure surrounding the power device are provided. The power device includes: a buried layer of a first conductivity type and a buried layer of a second conductivity type disposed within a substrate; a body region of the first conductivity type and a drift region of the second conductivity type disposed on the buried layer of the first conductivity type; and a gate electrode, a source electrode, and a drain electrode disposed on the body region of the first conductivity type and the drift region of the second conductivity type. The guard ring structure includes: a first guard ring of the second conductivity type adjacent to the power device; a second guard ring of the first conductivity type adjacent to the first guard ring; and a third guard ring of the second conductivity type adjacent to the second guard ring.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A switching LDMOS device is formed first well in a semiconductor substrate that includes an LDD region and a first body doped region; a first heavily doped region serving as a source region is provided in the LDD region, and a second heavily doped region serving as a drain region is provided in the first body doped region; a channel of the switching LDMOS device is formed at a surface layer of the semiconductor substrate between the LDD region and the body doped region and below the gate structure; and one side of the LDD region and one side of the body doped region which are away from the gate structure both are provided with a field oxide or STI, and one side of the field oxide or STI is in contact with the first heavily doped region or the second heavily doped region.

A light emitting apparatus comprising a plurality of pixels with different light emitting colors, each of the plurality of pixels includes a light-emitting element configured to emit light with one of at least three different light emitting colors, a driving transistor configured to supply a current to the light-emitting element in accordance with a voltage supplied to a gate, a write transistor configured to supply a signal voltage from a signal line to the gate of the driving transistor, and a capacitance at a connection portion between the driving transistor and the write transistor, wherein the capacitance is different for each light emitting color, and is larger in a pixel of a light emitting color in which a peak current flowing through the light-emitting element is larger.