A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.

A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.

In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

A semiconductor manufacturing apparatus according to the present embodiment includes a stage on which a wafer can be placed. A separator separates a beam of impurities to be introduced into the wafer into an ion component and a neutral component. A controller switches the semiconductor manufacturing apparatus between a first mode and a second mode, where in the first mode, the ion component is introduced into the wafer and in the second mode, the neutral component is introduced into the wafer.

A first high voltage semiconductor element, disposed in a substrate, includes first trenches; a first source region and a first drain region; first drift regions having respective ones partially surround the first source region and the first drain region; a first gate insulating layer and a first gate electrode disposed between the first drift regions; and a first high voltage well surrounding the first drift regions. A second high voltage semiconductor element, disposed in the substrate, includes second trenches; a second source region and a second drain region; second drift regions having respective ones partially surround the second source region and the second drain region; a second gate insulating layer and a second gate electrode disposed between the second drift regions; and a second high voltage well surrounding the second drift regions. Depths of the second trenches are disposed to be greater than depths of the first trenches.

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.