A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

The present invention provides an image pickup device that recognizes the object that the user is attempting to capture as the subject, tracks the movement of that subject, and can continue tracking the movement of the subject even when the subject leaves the capturing area so that the subject can always be reliably brought into focus. The image pickup device includes a main camera that captures the subject; an EVF that displays the captured image captured by the main camera, a sub-camera that captures the subject using a wider capturing region than the main camera, and a processing unit that extracts the subject from the captured images captured by the main camera and the sub-camera, tracks the extracted subject, and brings the subject into focus when an image of the subject is actually captured. When the subject moves outside of a capturing region of the main camera, the processing unit tracks the subject extracted from the captured image captured by the sub-camera.

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A semiconductor device including a substrate having a drain region therein is provided. A gate-electrode layer is disposed on the drain region. A first field-plate conductor is disposed on the substrate and overlaps the drain region. A gap is located laterally between the first field-plate conductor and the gate-electrode layer. A second field-plate conductor covers the first field-plate conductor and the gap. The second field-plate conductor is separated from the first field-plate conductor. A method for forming the semiconductor device is also provided.

Methods for forming transistors are provided. A substrate is placed in a processing chamber, and a plurality of epitaxial features is formed on the substrate. The epitaxial feature has at least a surface having the (110) plane and a surface having the (100) plane. An etchant or a gas mixture including an etchant and an etch enhancer or an etch suppressor is introduced into the processing chamber to remove a portion of the epitaxial feature. Etch selectivity between the surface having the (110) plane and the surface having the (100) plane can be tuned by varying the pressure within the processing chamber, the ratio of the flow rate of the etchant or gas mixture to the flow rate of a carrier gas, and/or the ratio of the flow rate of the etch enhancer or suppressor to the flow rate of the etchant.

The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.

A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-”shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.