Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

A method according to the present disclosure includes depositing, over a substrate, a stack including channel layers interleaved by sacrificial layers, forming a first fin structure and a second fin in a first area and a second area of the substrate, depositing a first dummy gate stack over the first fin structure and a second dummy gate stack over the second fin structure, recessing source/drain regions of the first fin structure and second fin structure to form first source/drain trenches and second source/drain trenches, selectively and partially etching the sacrificial layers to form first inner spacer recesses and second inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, and forming second inner spacer features in the second inner spacer recesses. A composition of the first inner spacer features is different from a composition of the second inner spacer features.

A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and semiconductor material layers stacked along a first direction over the substrate and spaced apart from each other. The semiconductor structure also includes inner spacers stacked along the first direction in spaces between the semiconductor material layers and a gate structure extending along a second direction and wrapping around the semiconductor material layers. In addition, the gate structure abuts a first side of the inner spacers. The semiconductor structure also includes a source/drain structure formed over the isolating feature and abutting the second side of the inner spacers.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide; a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride; a third semiconductor region of first conductivity type provided on the first semiconductor region; a fourth semiconductor region of first conductivity type provided on the second semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.

An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.