Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Methods and devices of providing tensile/compressive stressor layers for gate-all-around devices. A first GAA device and a second GAA are disposed having a shallow trench isolation feature and one of more stressor layers between gate structures of the first GAA device and the second GAA. The stressor layers can provide tensile stress to a channel layer of the first GAA device and a compressive stress to another channel layer of the second GAA device.

Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

A method of forming a semiconductor device includes soaking a batch of wafers in a first cleaning liquid, replacing the first cleaning liquid with a second cleaning liquid, soaking the batch of wafers in the second cleaning liquid, and soaking the batch of wafers in an etchant. The first cleaning liquid has a first temperature. The second cleaning liquid has a second temperature. The etchant has a third temperature. The second temperature is between the first temperature and the third temperature.

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

The performance of a transistor is improved. The semiconductor device according to the embodiment includes: an insulating film (12) that separates an n-type transistor formation region (Tr1) and a p-type transistor formation region (Tr2) from each other, in which each of the n-type transistor formation region and the p-type transistor formation region includes a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction, and a distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction is different between the n-type transistor formation region and the p-type transistor formation region.