A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

A manufacturing method of the semiconductor structure including the following is provided. Gate structures are formed on a substrate. Each gate structure includes a gate, a first spacer, and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, and the second spacers are separated from each other. A protective layer is formed between the two adjacent gate structures. The protective layer covers lower portions of the second spacers and exposes upper portions of the second spacers. A part of the upper portions of the second spacers is removed using the protective layer as a mask to enlarge a distance between the upper portions of the second spacers. The protective layer is removed.

A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.

The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.

A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.

A method of forming a semiconductor structure includes: providing a substrate including an upper surface, a gate structure disposed on the upper surface, a spacer disposed on a sidewall of the gate structure, a first region in the substrate, and a second region in the substrate; masking the second region and amorphizing the first region, such that an amorphous layer is formed in the first region; depositing a stress layer on the substrate, wherein the stress layer conformally covers the gate structure, the spacer, the first region and the second region; and recrystallizing the amorphous layer, thereby forming a dislocation in the first region.

Disclosed are a growth structure for a strained channel, and a strained channel using the same and a method of manufacturing a device using the same. The growth structure for a strained channel includes a support substrate, a strain-relaxed buffer (SRB) layer disposed on a support substrate, a base growth layer grown to have one composition on the SRB layer, and a strained channel layer grown to have another composition on the base growth layer. The strained channel layer may include at least one of a tensile-strained channel layer or a compressively strained channel layer.

A method of making a Fin Field-effect transistor includes: providing a substrate and a plurality of fin structures on a surface of the substrate; forming a shallow trench isolation structure between the plurality of fin structures; forming a stress layer on a side of the shallow trench isolation structure away from the substrate; heat treating the stress layer and the plurality of fin structures; and removing the stress layer. The fin structures are spaced apart from each other. The stress layer covers a part of the fin structures away from the substrate.

A method for modifying a strain state of at least one semiconductor layer includes providing a support over which is arranged at least one stack of layers including the semiconductor layer and a fusible layer, arranged between the semiconductor layer and the support. The method also includes melting at least one portion of the fusible layer the passage of said at least one portion of the fusible layer from a solid state into a liquid state, the semiconductor layer remaining in the solid state during the melting step. A laser beam may be used for the melting. The melting with the laser beam may also cause the modification of the strain state of the semiconductor layer.