A gate-all-around transistor device includes a substrate, and a layer over the substrate, where the layer includes an insulator material. The device also includes a source region and a drain region, and a body that includes a semiconductor material over the layer and that laterally extends between the source and drain regions. In an example, the semiconductor material of the body is under biaxial tensile strain induced by an underlying strained semiconductor on insulator (SSOI) structure, in addition to any additional strain induced by the source and drain regions (if any). A gate structure is at least in part wrapped around the body, where the gate structure includes (i) a gate electrode and (ii) a gate dielectric between the body and the gate electrode. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

A semiconductor device including at least one semiconductor device on a first surface of a dielectric layer, and at least one stressor structure having an intrinsic stress on a second surface of the dielectric layer. The at least one semiconductor device and the at least one stressor structure are present on opposing sides of the dielectric layer. The at least one stressor structure induces a stress on the at least one semiconductor device opposite the intrinsic stress.

Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.