A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.

A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.

An improvement is achieved in the reliability of a semiconductor device. In a memory cell region, a plurality of fins are provided which are portions of a semiconductor substrate extending in an x-direction along a main surface of the semiconductor substrate and spaced apart from each other in a y-direction orthogonal to the x-direction along the main surface of the semiconductor substrate. Between the fins adjacent to each other in the y-direction, a portion of an upper surface of an isolation region is at a position higher than a surface obtained by connecting a position of the upper surface of the isolation region which is in contact with a side wall of one of the fins to a position of the upper surface of the isolation region which is in contact with a side wall of the other fin. In a cross section along the y-direction, the upper surface of the isolation region has a projecting shape.

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.