A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.

A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.