Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.

A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Embodiments described herein may be related to creating a low resistance electrical path within a transistor between a front side trench connector and back side contacts and/or metal layers of the transistor. The low resistance electrical path does not go through a fin of the transistor that includes epitaxial material, but rather may go through a conductive path that does not include an epitaxial material. Embodiments may be compatible with a self-aligned back side contact architecture, which does not rely on deep via patterning. Other embodiments may be described and/or shown.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece that has a substrate, a first plurality of channel members, a second plurality of channel members, a first gate structure engaging the first plurality of channel members, a second gate structure engaging the second plurality of channel members, a hybrid fin disposed between the first and second gate structures, and an isolation feature disposed under the hybrid fin. The method also includes forming a metal cap layer at a frontside of the workpiece. The metal cap layer electrically connects the first and second gate structures. The method also includes etching the isolation feature, etching the hybrid fin, etching the metal cap layer, and depositing a dielectric material to form a gate isolation feature disposed between the first and second gate structures.

An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.

A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.