Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.

A semiconductor device includes a substrate; first and second fins protruding from the substrate; a first transistor including the first fin; a second transistor above the first transistor; and a first power supply line electrically connected to the first fin through the second fin. The first transistor includes first and second impurity areas in the first fin, and a first gate insulating film on the first fin between the first and second impurity areas. The second transistor includes a first semiconductor area above the first fin, a third impurity area in the first semiconductor area above the first impurity area, a fourth impurity area in the first semiconductor area above the second impurity area, and a second gate insulating film on the first semiconductor area between the third and fourth impurity areas. The first and second transistors have a common gate on the first and second gate insulating films.

A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

An IC structure comprises first, second, and third circuits. The first circuit comprises a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit comprises a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit comprises a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.

A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.

Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si.sub.3N.sub.4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.