An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.

A semiconductor device is provided. The semiconductor device includes a substrate, a first active pattern, which extends in a first direction on the substrate, a second active pattern, which extends in the first direction on the substrate and is spaced apart from the first active pattern by a first pitch in a second direction different from the first horizontal direction, a third active pattern, which extends in the first direction on the substrate and is spaced apart from the second active pattern by a second pitch greater than the first pitch in the second direction, a field insulating layer, which borders side walls of each of the first to third active patterns, a dam, which is between the first active pattern and the second active pattern on the field insulating layer, the region between the second active pattern and the third active pattern being free of the dam, a gate electrode, which extends in the second direction, and has a first portion on the first active pattern, a second portion on the second active pattern, and a third portion on the third active pattern, a first work function layer between the first portion of the gate electrode and the dam, and a second work function layer between the second portion of the gate electrode and the dam.

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.

An integrated circuit including a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a body region. The source region includes an outer region having a first conductivity type complementary to a second conductivity type of an outer region of the body and an interior-positioned conductive region having the second conductivity type.