Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.

Semiconductor devices having improved electrical characteristics are described, as are methods of fabricating the same. The semiconductor device may include a first gate electrode on a substrate and extending in a first direction, a second gate electrode on the substrate and running across the first gate electrode while extending in a second direction, and a channel structure between the second gate electrode and lateral surfaces in the second direction of the first gate electrode and between the second gate electrode and a top surface of the first gate electrode. The channel structure may include a first dielectric layer that covers in contact with the lateral surfaces and the top surface of the first gate electrode; a second dielectric layer on the first dielectric layer and in contact with the second gate electrode; and a channel layer between the first dielectric layer and the second dielectric layer.

A semiconductor device structure is provided. The semiconductor device structure includes a first metal gate stack and a second metal gate stack over a semiconductor substrate. The semiconductor device structure also includes a dielectric layer surrounding the first metal gate stack and the second metal gate stack. The semiconductor device structure further includes an insulating structure between the first metal gate stack and the second metal gate stack. The insulating structure has a first convex surface facing towards the first metal gate stack.

A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

A semiconductor device including a structure having N gate electrode layers G and (N−1) channel formation region layers CH (where N≥3) alternately juxtaposed on an insulating material layer of a base having the insulating material layer formed on a surface of a conductive substrate. Each of the structure, the channel formation region layer CH, and the gate electrode layer G has a bottom surface, a top surface, and four side surfaces. A second surface of the nth channel formation region layer is connected to a fourth surface of the nth gate electrode layer. A fourth surface of the nth channel formation region layer is connected to a second surface of the (n+1)th gate electrode layer. One of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion.