Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.

An integrated circuit includes a semiconductor substrate having a first type of conductivity and a semiconductor component. The semiconductor component includes: a buried semiconductor region having a second type of conductivity opposite to the first type of conductivity; a first gate region and a second gate region each extending in depth from a front face of the semiconductor substrate to the buried semiconductor region; a third gate region extending in depth from the front face of the semiconductor substrate and being electrically connected to the buried semiconductor region; and an active area delimited by the first gate region, the second gate region and the buried semiconductor region.

A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.

The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.