Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

In a described example, an integrated circuit includes a substrate of a semiconductor material, a source region, a gate region, a drain region and a fin structure formed on the substrate. The fin structure includes the gate region, the source region and a drift region between the gate region and the drain region. A doped control layer is formed along at least one sidewall of the fin structure over the drift region.

A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.

A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.

A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.

In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.

A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.