A 3D semiconductor device, the device including: a first level including a single crystal layer, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the second metal layer, where the second metal layer is significantly thicker than either the third metal layer or the first metal layer, where the third metal layer is precisely aligned to the first metal layer with less than 20 nm misalignment; a second level including a first array of first memory cells, each of the first memory cells include first transistors; a third level including a second array of second memory cells, each of the second memory cells include second transistors, where the second level is above the third level, where the second transistors are self-aligned to the first transistors, being processed following the same lithography step; and periphery circuits connected by the second metal to control the memory cells, where the periphery circuits are either underneath or atop the memory cells.

Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.

A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

A method of manufacturing a semiconductor device includes implanting a channel region of a first transistor and a channel region of a second transistor to have a first conductivity type. The method further includes forming source/drain regions of the first transistor to have the first conductivity type and source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type. The method further includes depositing a first work function layer over the channel region of the first transistor. The method further includes depositing a second work function layer over the channel region of the second transistor, wherein the first work function layer includes a same material as the second work function layer.