A method is presented for temperature assisted programming of flash memory for neuromorphic computing. The method includes training a chip in an environment having a first temperature, adjusting the first temperature to a second temperature in the environment, and employing the chip for inference in the second temperature environment. The first temperature is about 125° C. or higher and the second temperature is about 50° C. or lower.

The present application discloses a method for making an active area air gap, comprising: step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein each word line structure spans each field oxide and each active area; step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner; step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap; and step 4, removing the protective spacer.

Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.

A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack (11-18) of alternating Si and SiGe layers which are selectively processed to form epitaxial source/drain regions (25A, 25B) and to form gate electrodes (33A-D) which replace the silicon germanium layers in the nanosheet transistor stack, and then selectively forming one or more insulated conductive electrode layers (e.g., 37/39, 25/55, 64/69) adjacent to the nanosheet transistor to define a capacitor or nonvolatile memory cell that is integrated with the nanosheet transistor.

A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.

A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact is a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.