A semiconductor apparatus includes first, second and third transistors integrated in a monocrystal chip. Both the first and second transistors are vertical devices, each having a source node, a gate node and a drain node. The source node of the first transistor electrically connects to a primary source pin, the source node of the second transistor to a sample pin, and the gate nodes of the first and the second transistors to a control-gate pin. The third transistor is a vertical JFET with a source node, a control node and a drain node. The source node of the third transistor electrically connects to a charge pin, and the control node of the third transistor to a charge-control pin. All of the drain nodes of the first, second and third transistors are electrically connected to a high-voltage pin.

A semiconductor heterostructure device includes a middle layer including an inner conducting channel and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) is within the outer current blocking region. The DHCBR includes a first depleting impurity specie including a Column II acceptor, and a second depleting impurity comprising oxygen which increases a depletion of the DHCBR so that the DHCBR forces current to flow into the conducting channel during electrical biasing under normal operation of the semiconductor heterostructure device.

A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

A new and useful p-type oxide semiconductor with a wide band gap and an enhanced electrical conductivity and the method of manufacturing the p-type oxide semiconductor are provided. A method of manufacturing a p-type oxide semiconductor including: generating atomized droplets by atomizing a raw material solution including iridium and a metal that is different from iridium and optionally contained; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base to form a crystal or a mixed crystal of a metal oxide including iridium.

A method of forming an electrical device is provided that includes a semiconductor device and a passive resistor both integrated in a same vertically orientated epitaxially grown semiconductor material. The vertically orientated epitaxially grown semiconductor material is formed from a semiconductor surface of a supporting substrate. The vertically orientated epitaxially grown semiconductor material includes a resistive portion and a semiconductor portion, in which the sidewalls of the resistive portion are aligned with the sidewalls of the semiconductor portion. A semiconductor device is formed on the semiconductor portion of the vertically orientated epitaxially grown semiconductor material. A passive resistor is present in the resistive portion of the vertically orientated epitaxially grown semiconductor material, the resistive portion having a higher resistance than the semiconductor portion.

A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.

An object is to provide a technology for enabling prevention of deterioration of characteristics of an oxide semiconductor device. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, a p-type oxide semiconductor layer, and an oxide layer. The p-type oxide semiconductor layer is disposed above the n-type gallium oxide epitaxial layer, contains an element different from gallium as a main component, and has p-type conductivity. The oxide layer is disposed between the n-type gallium oxide epitaxial layer and the p-type oxide semiconductor layer, and is made of a material different from gallium oxide and different at least partly from a material of the p-type oxide semiconductor layer.

A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.

An embodiment relates to a semiconductor component, comprising a semiconductor body of a first conductivity type comprising a voltage blocking layer and islands of a second conductivity type on a contact surface and optionally a metal layer on the voltage blocking layer, and a first conductivity type layer comprising the first conductivity type not in contact with a gate dielectric layer or a source layer that is interspersed between the islands of the second conductivity type.

A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.