Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

A semiconductor device includes a JFET and a MOSFET cascode-connected to each other such that a source electrode of the JFET is connected to a drain electrode of the MOSFET. The JFET is configured such that a breakdown voltage between a gate layer and a body layer is set lower than a breakdown voltage of the MOSFET.

A semiconductor device includes a semiconductor substrate having a first conductivity type, a drift layer of the first conductivity type coupled to the semiconductor substrate, a fin array having a first row of fins and a second row of fins on the drift layer, and a space between the first row of fins and the second row of fins. The first row of fins includes a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins includes a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance.

A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.

According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.

A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.

A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.