A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm.sup.2/Vs or more.

A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.

A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

The present invention provides a Group III nitride semiconductor device in which current concentration at the corners of the trench is suppressed. The semiconductor device has a pattern in which regular hexagonal unit cells are arranged in a honeycomb pattern. The semiconductor layer is sectionalized into regular hexagonal patterns by the trench. The recess has a small regular hexagonal pattern contained in the regular hexagonal pattern of the semiconductor layer sectionalized by the trench, which is obtained by reducing the regular hexagon of the semiconductor layer with the same center. Moreover, the regular hexagonal pattern of the recess is rotated by 30 with respect to the regular hexagon of the semiconductor layer. The Mg activation ratio is lower in the vicinity of corners of the trench than that in other regions in the vicinity of side walls of the trench of the p-type layer.

An industrially useful p-type oxide semiconductor with an enhanced semiconductor characteristic and a method of forming the p-type oxide semiconductor is provided. By using a metal oxide (for example, iridium oxide) gas as a raw material and conducting a crystal growth on a base with a corundum structure (for example, a sapphire substrate) until a film thickness to be equal to or more than 50 nm, a p-type oxide semiconductor film with a corundum structure includes a film thickness of equal to or more than 50 nm and a surface roughness of equal to or less than 10 nm is obtained.