A cell structure for a field effect transistor having same gate and source doping includes: a silicon carbide substrate with a doping type of a first conductivity type; a semiconductor epitaxial layer of the first conductivity type and a first electrode respectively provided on front and back faces of the silicon carbide substrate; and a floating region of a second conductivity type, a gate implantation region of the first conductivity type, and a source implantation region of the first conductivity type sequentially provided on the semiconductor epitaxial layer of the first conductivity type, wherein a gate is provided on the gate implantation region, a source is provided on the source implantation region, an inter-electrode dielectric is provided between the gate implantation region and the source implantation region, and the inter-electrode dielectric is used for isolating the gate from the source.

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO.sub.2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO.sub.2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Electronic devices are formed on donor substrates and transferred to carrier substrates by forming bonding regions on the electronic devices and bonding the bonding regions to a carrier substrate. The transfer process may include forming anchors and removing sacrificial regions.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.

A multilayer structure with excellent crystallinity and a semiconductor device of the multilayer structure with good mobility are provided. A multilayer structure includes: a corundum structured crystal substrate; and a crystalline film containing a corundum structured crystalline oxide as a major component, the film formed directly on the substrate or with another layer therebetween, wherein the crystal substrate has an off angle from 0.2° to 12.0°, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium.

A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×10.sup.14 cm.sup.−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.