A MESFET transistor on a horizontal substrate surface with at least one wiring layer on the substrate surface. The transistor comprises source, drain and gate electrodes which are at least partly covered by a semiconducting channel layer. The source, drain and gate electrodes optionally comprise interface contact materials for changing the junction type between each electrode and the channel. The interface between the source electrode and the channel is an ohmic junction, the interface between the drain electrode and the channel is an ohmic junction, and the interface between the gate electrode and the channel is a Schottky junction. The substrate is a CMOS substrate.

Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.

A Ga.sub.2O.sub.3-based semiconductor element includes an undoped -Ga.sub.2O.sub.3 single crystal film disposed on a surface of a -Ga.sub.2O.sub.3 substrate, a source electrode and a drain electrode disposed on a same side of the undoped -Ga.sub.2O.sub.3 single crystal film, a gate electrode disposed on the undoped -Ga.sub.2O.sub.3 single crystal film between the source electrode and the drain electrode, and a region formed in the undoped -Ga.sub.2O.sub.3 single crystal film under the source electrode and the drain electrode and including a controlled dopant concentration.

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.