A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

A structure includes a controlled polyimide profile. A method for forming such a structure includes depositing, on a substrate, a photoresist containing polyimide and performing a first anneal at a first temperature. The method further includes exposing the photoresist to a radiation source through a photomask having a pattern associated with a shape of a polyimide opening. The method further includes performing a second anneal at a second temperature and removing a portion of the photoresist to form the polyimide opening. The method further includes performing a third anneal at a third temperature and cleaning the polyimide opening by ashing.

A semiconductor apparatus including a bonding region in which a wire is bonded, includes: a semiconductor substrate; an oxide film provided on a principal surface of the semiconductor substrate in the bonding region; a polysilicon layer provided on the oxide film; an interlayer film partially provided on the polysilicon layer; a barrier metal directly provided on the polysilicon layer and the interlayer film; and an electrode provided on the barrier metal.

An interposer according to an embodiment of the present invention includes a base layer having opposite first and second surfaces, a wiring structure on the first surface of the base layer, an interposer protective layer disposed on the second surface of the base layer and having a pad recess with a lower surface of the interposer protective layer positioned at a first vertical level and a bottom surface of the pad recess positioned at a second vertical level that is higher than the first vertical level, an interposer pad of which a portion fills the pad recess of the interposer protective layer and the remaining portion protrudes from the interposer protective layer, and an interposer through electrode extending through the base layer and the interposer protective layer to the interposer pad, the interposer through electrode electrically connecting the wiring structure to the interposer pad.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

A semiconductor apparatus including a bonding region in which a wire is bonded, includes: a semiconductor substrate; an oxide film provided on a principal surface of the semiconductor substrate in the bonding region; a polysilicon layer provided on the oxide film; an interlayer film partially provided on the polysilicon layer; a barrier metal directly provided on the polysilicon layer and the interlayer film; and an electrode provided on the barrier metal.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

The present application provides a method for preparing a semiconductor device, include the following steps: forming a source/drain (S/D) region in a semiconductor substrate; forming a bonding pad over the semiconductor substrate; forming a first spacer over a sidewall of the bonding pad; forming a first passivation layer covering the bonding pad and the first spacer; and forming a conductive bump over the first passivation layer, wherein the conductive bump penetrates through the first passivation layer to electrically connect to the bonding pad and the S/D region.