A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

A chip package is provided. The chip package includes a first substrate including a sensing region or device region. The chip package also includes a second substrate. The first substrate is mounted on the second substrate and is electrically connected to the second substrate. The ratio of the thickness of the first substrate to the thickness of the second substrate is in a range from 2 to 8.

An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation with other integrated circuits realized on a same wafer. The integrated circuit includes at least one conductive structure that extends in the peripheral portion on different planes of metallizations starting from the substrate and forms an integrated antenna. Magnetic trench structures are provided adjacent the integrated antenna.

A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including a first pad, arranged along the second side and formed over a semiconductor substrate. The first pad is arranged nearer the corner than other pads of the plurality of pads. The first pad includes a third side, a fourth side being perpendicular to the third side, a fifth side being parallel to the third side and a sixth side being perpendicular to a fifth side. The third side and the fourth side are nearer to the corner than the fifth side and sixth side. A first dummy wiring is formed along the first side. A second dummy wiring is formed along the second side. The first dummy wiring and the second dummy wiring are formed integrally with each other.

The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.

A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an AlCu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the AlCu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure TEG realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.

A method for removing material from a substrate includes providing the substrate with first and second opposing major surfaces. A masking layer is disposed along one of the first major surface and the second major surface, and is provided with a plurality of openings. The substrate is placed within an etching apparatus and material is removed from the substrate through openings using the etching apparatus. The thickness of the substrate is measured within the etching apparatus using a thickness transducer. The measured thickness is compared to a predetermined thickness and the material removal step is terminated responsive to the measured thickness corresponding to the predetermined thickness. In one embodiment, the method is used to more accurately form recessed regions in semiconductor die, which can be used in, for example, stacked device configurations.

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

A stacked semiconductor device structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed surface portion bounded by opposing sidewall portions extending outward to define a recessed region. A conductive layer is disposed along at least the recessed surface portion. The second semiconductor device is disposed within the recessed portion and is electrically connected to the conductive layer. In one embodiment, the stacked semiconductor device is connected to a conductive lead frame and is at least partially encapsulated by a package body.