Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

A semiconductor device includes a semiconductor body; an electrode provided on the semiconductor body and electrically connected to the semiconductor body; a first metal layer selectively provided on the electrode; an insulating layer surrounding the first metal layer on the electrode; and a second metal layer provided on the first metal layer. The insulating layer includes a first surface and a second surface adjacent to the first surface. The first surface contacts a top surface of the first metal layer at an outer edge of the first metal layer. The second metal layer has an outer edge contacting the second surface of the insulating layer.

A electronic component includes a connection electrode on a wiring layer. An electrically conductive layer is connected to the wiring layer via the connection electrode. A protective film covers a cover portion and the electrically conductive layer. A solder bump is electrically connected to the electrically conductive layer via an opening. An alloy layer is between the solder bump and the electrically conductive layer in a thickness direction to join the solder bump to the electrically conductive layer and differs in composition and/or elements from the solder bump. The connection electrode does not overlap the solder bump. The surface of the electrically conductive layer that is located on a protective film side is in contact with the protective film between the alloy layer and an edge of the electrically conductive layer that is located on a connection electrode side.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

A stack package includes first and second sub-chip stacks stacked on a package substrate and bonding wires. The first sub-chip stack includes first and second sub-chips. The first sub-chip has a first surface on which a first common pad is disposed. The second sub-chip has a third surface on which a second common pad is disposed. The third surface is bonded to the first surface such that the second common pad is bonded to the first common pad. The second sub-chip includes a fourth surface opposite to the second common pad and a through hole extending from the fourth surface to reveal the second common pad. The bonding wire is connected to the second common pad via the through hole and electrically connects both of the first and second common pads to the package substrate.

In a described example, a method is described including: depositing a zinc seed layer on a substrate; forming a photoresist pattern on the zinc seed layer, with openings in the photoresist pattern exposing portions of the zinc seed layer; electroplating a copper structure onto the exposed portions of the zinc seed layer; stripping the photoresist; annealing the substrate to form copper/zinc alloy between the copper structure and the substrate; and etching away the unreacted portions of the zinc seed layer.

An apparatus and method for reducing the volume of a resource allocation information message in a broadband wireless communication system are provided. The method includes transmitting a message including information indicating a periodicity of an uplink control channel for an initial network entry; and receiving an uplink signal for the initial network entry through the uplink control channel.