Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

A testing architecture for integrated circuits on a wafer includes at least one first circuit of a structure TEG realized in a scribe line providing separation between first and second integrated circuits. At least one pad is shared by a second circuit inside at least one of the first and second integrated circuits and the first circuit. Switching circuitry is coupled to the at least one pad and to the first and second circuits.

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.

A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.

A package structure including an insulating encapsulation, at least one semiconductor die, at least one first antenna and at least one second antenna is provided. The insulating encapsulation includes a first portion, a second portion and a third portion, wherein the second portion is located between the first portion and the third portion. The at least one semiconductor die is encapsulated in the first portion of the insulating encapsulation, and the second portion and the third portion are stacked on the at least one semiconductor die. The at least one first antenna is electrically connected to the at least one semiconductor die and encapsulated in the third portion of the insulating encapsulation. The at least one second antenna is electrically connected to the at least one semiconductor die and encapsulated in the second portion of the insulating encapsulation.

A semiconductor die includes a last metallization layer above a semiconductor substrate, a bond pad above the last metallization layer, a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad, an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad, and an electrically conductive interconnection structure that extends from the bond pad to the upper metallization layer outside the contact area of the bond pad. Corresponding methods of manufacture are also provided.

A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.

A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.