A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.

In order to inhibit forming cracks under a pad opening during ball bonding without increasing a chip size, a protective film includes a pad opening that exposes a part of a topmost layer metal film. A second metal film provided under the pad opening has a ring shape that defines a rectangular opening under the pad opening. The opening edge of the opening in the second metal film extends inwardly beyond the edge of the overlying pad opening.

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL).

In a wafer inspection step for testing electrical characteristics of an integrated circuit in a chip region (CP) formed in a wafer, a first probe needle having a relatively small diameter is brought into contact with a first pad for small current and a second probe needle having a relatively large diameter is brought into contact with a second pad for large current. A wiring and a field effect transistor, which are used for forming the integrated circuit, are arranged directly under the first pad to which a relatively small needle pressure of the first probe needle is to be applied. On the other hand, a wiring and a field effect transistor, which are used for forming the integrated circuit, are not arranged directly under the second pad to which a relatively large needle pressure of the second probe needle is to be applied.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A conductive structure is disposed on the conductive pad, and a passive device is also disposed on the conductive pad, wherein the passive device has a first portion located above the second passivation layer and a second portion passing through the second passivation layer. A solderability preservative film covers the first portion of the passive device, and an under bump metallurgy (UBM) layer covers the second portion of the passive device and a portion of the conductive structure.