A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.

Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.

A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.