The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, contains nickel or copper, and is electrically connected to the semiconductor device; a solder portion containing gold, disposed on the bonding layer; and a protective layer disposed directly on the bonding layer, covering an outer peripheral edge of the bonding layer.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

A semiconductor package includes a semiconductor chip, and including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad of the semiconductor chip and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening, an encapsulant covering at least a portion of the semiconductor chip, and a connection structure disposed on the active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via. The second opening has a width narrower than a width of the first opening.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.

A portion of a source electrode exposed by an opening in a passivation film is used as a portion of a source pad. A first portion of the source pad includes a plating film formed by a material that is harder than a material of the source electrode. During screening, a probe needle that is a metal contact contacts the plating film that is on the first portion of the source pad. A second portion of the source pad has a layer structure different from that of the first portion of the source pad and in a second direction parallel to the front surface of the semiconductor chip, is disposed adjacently to and electrically connected to the first portion of the source pad. A bonding wire is wire bonded to the second portion of the source pad after an inspection process of the semiconductor chip.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.

A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.