A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; , a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

There is set forth herein a method including building a first photonics structure using a first wafer having a first substrate, wherein the building the first photonics structure includes integrally fabricating within a first photonics dielectric stack one or more photonics device, the one or more photonics device formed on the first substrate; building a second photonics structure using a second wafer having a second substrate, wherein the building the second photonics structure includes integrally fabricating within a second photonics dielectric stack a laser stack structure active region and one or more photonics device, the second photonics dielectric stack formed on the second substrate; and bonding the first photonics structure and the second photonics structure to define an optoelectrical system having the first photonics structure bonded the second photonics structure.

In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component parts to each other by a direct bonding process at the contact layers.

A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip. A first conductive connection wire of the first chip is connected to a first conductive contact pad, and a second conductive connection wire of the second chip is connected to a second conductive contact pad. In addition, the first conductive contact pad includes a first conductor group and a second conductor group, and the second conductive contact pad includes a third conductor group and a fourth conductor group.

A semiconductor structure is provided. The semiconductor structure includes a first substrate, and a first bonding structure and a first conductive via which are formed in the first substrate. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than a melting point of the first metal layer. The first metal layer includes a first surface and a second surface arranged opposite to each other. The first surface of the first metal layer is provided with a first groove, and the second metal layer is arranged in the first groove. The first conductive via is in contact with the second surface of the first metal layer. A projection of the first conductive via coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.

An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

Disclosed is a semiconductor device comprising a substrate including a first surface and a second surface that are opposite to each other, a via structure that penetrates the substrate, a first passivation pattern disposed on the first surface of the substrate and extending onto an upper sidewall of the via structure, and a second passivation pattern disposed on the first passivation pattern and exposing an uppermost surface of the first passivation pattern. At least a portion of the second passivation pattern is externally exposed. The first passivation pattern includes at least one selected from oxide and silicon oxide. The second passivation pattern includes at least one selected from nitride and silicon nitride.