A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern.

A semiconductor device having an electrode type of the ball grid array (BGA) and a process of forming the electrode are disclosed. The electrode insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

A semiconductor device includes a semiconductor substrate including a main chip region and a remaining scribe lane region surrounding the main chip region, a passivation layer on the main chip region, the passivation layer including a plurality of bridge patterns extending from the main chip region in a first direction across the remaining scribe lane region, a plurality of bump pads exposed by the passivation layer on the main chip region, a plurality of dam structures along edges of the main chip region on the remaining scribe lane region, the plurality of bridge patterns arranged on the plurality of dam structures at a first pitch in the first direction, a seed layer on the plurality of bump pads, and bumps on the seed layer.

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.